圧縮伸張バッファ回路

Compression/expansion buffer circuit

Abstract

PROBLEM TO BE SOLVED: To effectively utilize a FIFO memory and to perform the efficient conversion of continuous data sequences with burst signals by sharing the same FIFO memory for transmission and reception. SOLUTION: This compression/expression buffer circuit is provided with the FIFO memories 11-1 to 11-n is common for which write and read are provided with different clock speeds. Then, by the respective FIFO memories 11-1 to 11-n, the continuous digital data sequences are converted to the burst signals for performing the transmission by a TDMA system and the burst signals received by the TDMA system are converted to the continuous digital data sequences. In this case, the number of the FIFO memories 11-1 to 11-n corresponds to a burst number included in one frame of the TDMA system and a selector 12 and switches 13 and 14 are provided so as to switch the FIFO memories 11-1 to 11-n respectively corresponding to bursts allocated for the transmission and the bursts allocated for the reception in the frame.
(57)【要約】 【課題】 TDMA方式の通信において、連続データ列 とバースト信号とを変換するFIFOメモリの使用効率 を高める。 【解決手段】 送信と受信とで同一のFIFOメモリ1 1−1〜11−nを共用し、その動作を送信時と受信時 とで切り替える。

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